The present invention relates to an apparatus which computes the linear address of an instruction using a threeport adder in a microprocessor.
In order to execute an instruction, the microprocessor must first fetch the instruction from its location in memory. Instructions in memory are stored at their physical address. Typically, in a microprocessor system using paging and segmentation of its memory, the physical address is computed in a series of steps. First, the effective address is calculated. The effective address is calculated by the addition of the base address value within a segment to the displacement value. Second, the linear address is calculated by adding the segment base address value to the effective address. Finally, the linear address is translated into the required physical address using a Translation Lookaside Buffer.
Microprocessors have different standard address lengths. A microprocessor may use an address length of 16 bits or 32 bits, for example. Typically the paging and segmentation portion of the address are assigned the higher order bits.
FIG. 1 shows a block diagram of the standard logic configuration 110 used to calculate the linear address in a 16-bit mode in the Intel 8086. Computation of the linear address is accomplished in two steps. First, the base address value on a bus 112 and the displacement value on a bus 114 are added in a two-port adder 116. In the configuration shown, the addition of the 16-bit displacement value and 16-bit base address value are output onto a 16-bit bus 118. Therefore, if the addition of the base address value and displacement value results in a value over 16 bits, modulo arithmetic is performed so that the effective address value is truncated and the carry bits are lost. The truncation of the effective address value results in a wrap around of the effective address value so that it points within the 64 K memory boundary.
In the second stage of calculating the linear address value, the 16-bit effective address on bus 118 is zero extended by bus 120 to result in a 20-bit bus 122 which is then added to a 20-bit segment base on bus 128. In the actual Intel 8086 design, the 16-bit segment base on bus 126 is shifted left by four bits as shown by bus 124. This results in a 20-bit bus 128. Bus 128 is then added to the 20-bit bus 122 by a 20-bit adder 130 so that the addition of the segment base value to the effective address results in a 20-bit output value on bus 132.
FIG. 2 illustrates the wraparound which occurs in 16-bit mode when the sum (the effective address) and the operand are both 16-bit values, and the calculation of the effective address results in a value which would be greater than 16 bits had additional bits been allocated for output. For example, if the base address value is (2.sup.16 -1) and the displacement value is 11, the effective address is not ((2.sup.16 -1)+11). Instead the effective address is truncated so that it is within the allocated 16 bit positions. Since only 16-bit positions exist, the carry bit is lost and the effective address wraps around so that it points to an effective address of 10.
FIG. 3 shows a three-port 32-bit adder 326 which may be used in a modern 32-bit address architecture. The adder has two parts. A three-port carry save adder first stage 328 produces a sum and carry bit for each bit position. A second stage two-port adder 330 takes the 32 sum bits and 32 carry bits, propagates the carry and produces a 32-bit sum as its output. The adder cannot only generate 32-bit addresses but can also, in a 16-bit mode, produce 16-bit addresses (or 20 bits for the Intel 8086 extended addressing). This is important because many users have programs for machines using the Intel 8086 which they would like to run on a new 32-bit machine.
A compatibility problem arises, however, because the 16-bit truncation of FIG. 1 is no longer present. The carry from the 16th bit is simply added in with the rest of the result. For example, if the base address is 65,535 ((64K-1) or (2.sup.16 -1)) and the displacement is 11, there will be wraparound in the first stage of FIG. 1, giving an effective address of 10. If this effective address is added to a segment base of 8192, the result is 8,202. Using the 32-bit adder of FIG. 3 this intermediate truncation will not occur. Instead, the 32-bit adder will simply add 65,535 to 11 and 8,192 giving a value 73,738 when the program was expecting a value of 8,202.